Entering 90 nm nodes, the strained silicon technique becomes a basic technique for improving MOSFET device performance by repressing short channel effect and increasing carrier mobility, wherein the following stress techniques are put forward, such as shallow trench isolation (STI) technique, stress proximity technique (SPT), source/drain region embedded SiGe technique, metal gate stress technique, and contact etch stop layer (CESL) technique.
At stages of 90 nm and 65 nm, for the PMOS source/drain region embedded SiGe technique employs a method that comprises such steps as performing dry etching to the source/drain region and then epitaxially growing SiGe in the resultant recess to provide the channel with a compressive stress thereby improving the performance of the PMOS. At stages 45 nm and 32 nm, a change is made to the etching of the source/drain region, i.e., using the spacer as a mask, first performing dry etching to the source/drain region to form a recess (as shown in FIG. 6a), then performing wet etching to the recess obtained from the above dry etching through such solutions as tetramethylammonium hydroxide (TMAH) to further form a Sigma shaped recess, as shown in FIG. 6b, wherein the bottom surface of the Sigma shaped recess is a {100} surface, whereas two inclined planes are a {111} surface, the start point of the {111} surface in FIG. 6b is substantially aligned with the outer edge of the spacer. Next, SiGe (e-SiGe) is epitaxially grown in the Sigma shaped recess. However, in the above method of forming a Sigma shaped recess, because it is necessary to perform dry etching to the source/drain region to form a deeper recess first, it is usually a requirement that the corresponding masking spacer should be fairly thick. Therefore, even if TMAH solution is employed thereafter to perform wet etching, because the etching start point is at the outer edge of the masking spacer, the Sigma shaped recess is relatively farther away from the channel. As a result, it is difficult to further improve the performance of the PMOS device.